FIG. 1 illustrates a typical hard disk drive 1500. Hard disk drive 1500 includes hard disk controller 1502 that controls the transfer of data between moving storage medium 1506 and host 1503, such as, for example, between a magnetic surface of a moving medium and a computer. Hard disk controller 1502 typically includes a host interface 1508 for communicating with host 1503, storage medium interface 1507 for writing data to and reading data from storage medium 1506, and a memory controller 1501 for controlling access to memory 1509 via a multi-channel bus 1504.
Memory 1509 functions as a cache for information to and from host 1503, and as temporary storage for data being written to or read from medium 1506. Hard disk controller 1502 arbitrates access to memory 1509, typically through time division delegation of access to the memory to plural different circuitry, each of which accesses the memory 1509 on behalf of its client. As two examples, there is channel zero (CH0) circuitry for performing a CH0 process to access memory 1509 on behalf of storage medium 1506, and channel one (CH1) Circuitry for Performing a CH1 Process to Access memory 1509 on behalf of host 1503. The multi-channel bus 1504 includes a CH0 channel to which the CH0 circuitry is connected and a CH1 channel to which the CH1 circuitry is connected.
FIG. 2 is a time-line illustrating the arbitration performed by controller 1502. Controller 1502 uses an arbitration algorithm to prevent different processes from accessing memory 1509 simultaneously. Within each arbitration round-trip, each process is assigned a “tenure” within which the process's corresponding channel of the multi-channel bus may access memory 1509. After a channel's tenure expires, the channel does not access memory 1509 until the next arbitration round-trip. FIG. 2 depicts these tenures, 110, 111, and 112, in one arbitration round-trip. Each of tenures 110 to 112 represent a maximum amount of time within which channels CH0, CH1, and CH2, respectively, may access memory 1509 to burst data (i.e., transfer data to/from memory 1509). An additional amount of time between each tenure (e.g., 120, 121, and 122) is reserved for memory control overhead operations such as, for example, initializing memory 1509 before a burst, processing commands stored in memory 1509, refreshing memory 1509, storing state information in memory 1509 before the end of a tenure, and any other suitable memory control overhead operations.
To maintain a specified data transfer rate, channel CH0 accesses memory 1509 to retrieve (or store) additional data before storage medium 1506 moves a distance corresponding to one sector of the disk. Because the CH0 process typically bursts data corresponding to one sector of storage medium 1506, the maximum time for arbitration round-trips is equal to the time 140 for storage medium 1506 to move a distance corresponding to one sector (i.e., one disk sector cycle) to ensure that the next tenure of the CH0 channel (e.g., 110) occurs before the next sector of storage medium 1506 is ready to be accessed. If the delay 130 between CH0 channel tenures 110 is too long, the next sector is missed, and the CH0 process must wait for the sector to move back into position. The transfer rate thus decreases. Therefore, to maintain a specified data transfer rate, the arbitration round-trip time must not be greater than one disk sector cycle time 140.